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Integrated Circuit Systems, Inc.
ICS98ULPA877A Advance Information
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application: * DDR2 Memory Modules / Zero Delay Board Fan Out * Provides complete DDR2 DIMM logic solution Product Description/Features: * Low skew, low jitter PLL clock driver * 1 to 10 differential clock distribution (SSTL_18) * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * Auto PD when input signal is at a certain logic state Switching Characteristics: * Period jitter: 40ps (DDR2-400/533) 30ps (DDR2-667/800) * Half-period jitter: 60ps (DDR2-400/533) 50ps (DDR2-667/800) * OUTPUT - OUTPUT skew: 40ps (DDR2-400/533) 30ps (DDR2-667/800) * CYCLE - CYCLE jitter 40ps
Pin Configuration
1 A B C D E F G H J K 2 3 4 5 6
52-Ball BGA
Top View
A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4
CLKC1 CLKC0 CLKT1
Block Diagram
OE OS AVDD LD or OE POWER DOWN AND LD, OS, or OE TEST MODE PLL BYPASS LOGIC LD
(1)
3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4
CLKC5 CLKT0 VDDQ
4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9
CLKT5 CLKC6 CLKT6
5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9
VDDQ
6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8
CLKT0
39
32
35
34
37
40
CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4
38
36
33
31
CLKC0
VDDQ CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND
1 2 3 4 5 6 7 8 9 10
16 17 13 11 12 15 18 14 19 20
30 29 28 27 26 25 24 23 22 21
CLKC7 CLKT7 VDDQ FB_INT FB_INC FBOUTC FBOUTT VDDQ OE OS
CLK_INT CLK_INC 10K - 100K FBIN_INT FBIN_INC PLL
CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8
VDDQ
CLKT3
CLKT4
CLKC3
CLKC4
CLKT9 CLKC9 NOTE: 1. The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK_INT and CLK_INC.
FBOUTT FBOUTC
40-Pin MLF
1177C--05/23/07
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
CLKC9
CLKC8
CLKT9
CLKT8
VDDQ
CLKC8
ICS98ULPA877A Advance Information
Pin Descriptions
Te r m i n a l Name AGND AVDD CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC OE OS GND VDDQ CLKT[0:9] CLKC[0:9] NB Analog Ground A n a l o g p ow e r Clock input with a (10K-100K Ohm) pulldown resistor Complentar y clock input with a (10K-100K Ohm) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output Output Enable (Asynchronous) Output Select (tied to GND or VDDQ) Ground Logic and output power Clock outputs Complementary clock outputs No ball Description Electrical Characteristics Ground 1.8 V nominal Differential input Differential input Differential input Differential input Differential output Differential output LVCMOS input LVCMOS input Ground 1.8V nominal Differential outputs Differential outputs
The PLL clock buffer, ICS98ULPA877A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF. ICS98ULPA877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. The PLL in ICS98ULPA877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS98ULPA877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
1177C--05/23/07
2
ICS98ULPA877A Advance Information
ICS98ULPA877A is available in Commercial Temperature Range (0C to 70C) and Industrial Temperature Range (-40C to +85C). See Ordering Information for details
Function Table
Inputs AVDD GND GND GND GND 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) OE H H L L L L H H X X OS X X H L H L X X X X CLK_INT L H L H L H L H L H CLK_INC H L H L H L H L L H CLKT L H *L(Z) *L(Z), CLKT7 active *L(Z) *L(Z), CLKT7 active L H *L(Z) CLKC H L *L(Z) *L(Z), CLKC7 active *L(Z) *L(Z), CLKC7 active H L *L(Z) Outputs PLL FB_OUTT L H L H L H FB_OUTC H L H L Bypassed/Off Bypassed/Off Bypassed/Off Bypassed/Off
H L
On On
L H *L(Z) Reser ved
H L *L(Z)
On On Off
*L(Z) means the outputs are disabled to a low stated meeting the IODL limit.
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ICS98ULPA877A Advance Information
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V GND - 0.5V to VDDQ + 0.5V -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
Commercial: TA = 0C - 70C; Industrial: TA = -40C - +85C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) SYMBOL MIN PARAMETER CONDITIONS Input High Current IIH VI = VDDQ or GND (CLK_INT, CLK_INC) Input Low Current (OE, IIL VI = VDDQ or GND OS, FB_INT, FB_INC) Output Disabled Low IODL OE = L, VODL = 100mV 100 Current CL = 0pf @ 410MHz IDD1.8 Operating Supply Current CL = 0pf IDDLD VIK VDDQ = 1.7V Iin = -18mA Input Clamp Voltage VDDQ - 0.2 IOH = -100 A VOH High-level output voltage IOH = -9 mA 1.1 IOL=100 A VOL Low-level output voltage IOL=9 mA VI = GND or VDDQ CIN 2 Input Capacitance1 1 COUT 2 VOUT = GND or VDDQ Output Capacitance
1
TYP
MAX 250 10
UNITS A A A
300 500 -1.2 1.45 0.25
0.10 0.6 3 3
mA A V V V V V pF pF
Guaranteed by design, not 100% tested in production.
1177C--05/23/07
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ICS98ULPA877A Advance Information
Recommended Operating Condition (see note1)
Commercial: TA = 0C - 70C; Industrial: TA = -40C - +85C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDDQ, AVDD 1.7 1.8 1.9 V CLK_INT, CLK_INC, FB_INC, 0.35 x V DDQ V FB_INT Low level input voltage VIL OE, OS 0.35 x V DDQ V CLK_INT, CLK_INC, FB_INC, 0.65 x VDDQ V FB_INT High level input voltage VIH OE, OS 0.65 x VDDQ V DC input signal voltage VIN -0.3 VDDQ + 0.3 V (note 2) DC - CLK_INT, CLK_INC, 0.3 VDDQ + 0.4 V Differential input signal FB_INC, FB_INT VID voltage (note 3) AC - CLK_INT, CLK_INC, V 0.6 VDDQ + 0.4 FB_INC, FB_INT Output differential crossVOX VDDQ/2 - 0.10 V DDQ/2 + 0.10 V voltage (note 4) Input differential crossVDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15 V VIX voltage (note 4) High level output current I OH -9 mA 9 mA Low level output current I OL Operating free-air TA -40 85 C temperature
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing.
1177C--05/23/07
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ICS98ULPA877A Advance Information
Timing Requirements
Commercial: TA = 0C - 70C; Industrial: TA = -40C - +85C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp dtin TSTAB 1.8V+0.1V @ 25C 1.8V+0.1V @ 25C 95 160 40
MAX 410 410 60 15
UNITS MHz MHz % s
NOTE: The PLL must be able to handle spread spectrum induced skew. NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters. NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode and later return to active operation. CK and CK# may be left floating after they have been driven low for one complete clock cycle.
1177C--05/23/07
6
ICS98ULPA877A Advance Information
Switching Characteristics
1
Commercial: TA = 0C - 70C; Industrial: TA = -40C - +85C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER CONDITION SYMBOL ten Output enable time OE to any output tdis OE to any output Output disable time Period jitter Half-period jitter Input slew rate Output clock slew rate Cycle-to-cycle period jitter Dynamic Phase Offset Static Phase Offset t jit (per) + t (O)dyn + t skew(o) t(O)dyn + tskew(o) Output to Output Skew SSC modulation frequency SSC clock input frequency deviation PLL Loop bandwidth (-3 dB from unity gain) tjit (per) tjit(hper)
SLr1(i) SLr1(o)
(MHz) 160 to 410 160 to 270 271 to 410 160 to 270 271 to 410
MIN
TYP 4.73 5.82
Input Clock Output Enable (OE), (OS) 160 to 410
tjit(cc+) tjit(cc-) t(O)dyn tSPO2 (su) t (h) tskew 160 to 270 271 to 410 271 to 410
-40 -30 -60 -50 1 0.5 1.5 0 0 -50 -20 -50
2.5 2.5
MAX 8 8 40 30 60 50 4 3 40 -40 50 20 50 80 60 40 30 33 -0.50
0
160 to 270 271 to 410 30.00 0.00 2.0
UNITS ns ns ps ps ps ps v/ns v/ns v/ns ps ps ps ps ps ps ps ps ps kHz % MHz
Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design.
1177C--05/23/07
7
ICS98ULPA877A Advance Information
Parameter Measurement Information
VDD
ICS98ULPA877A V(CLK)
V(CLK)
GND
Figure 1: IBIS Model Output Load
VDD/2 C = 10pF GND
ICS98ULPA877A
SCOPE
Z = 60 L = 2.97" Z = 120 Z = 60 L = 2.97" C = 10pF
R = 10
Z = 50 R = 1M C = 1pF
R = 10
Z = 50
VTT R = 1M C = 1pF VTT Note: VTT = GND
GND VDD/2
Figure 2: Output Load Test Circuit
Yx, FB_OUTC
Yx, FB_OUTT tC(N) tJIT(CC) = tC(N) + tC(N + 1) tC(N + 1)
Figure 3: Cycle-to-Cycle Jitter
1177C--05/23/07
8
ICS98ULPA877A Advance Information
Parameter Measurement Information
CLK_INC
CLK_INT
CLK_INC
CLK_INT t()n n=N t() = 1 N Figure 4: Static Phase Offset t()n t()n+1
Yx#
Yx
Yx, FB_OUTC
Yx, FB_OUTT tSKEW
Figure 5: Output Skew
Yx, FB_OUTC
Yx, FB_OUTT tC(n) Yx, FB_OUTC
Yx, FB_OUTT 1 fo
t(JIT_PER) = tC(n) -
1 fo
Figure 6: Period Jitter
1177C--05/23/07
9
ICS98ULPA877A Advance Information
Parameter Measurement Information
Yx, FB_OUTC
Yx, FB_OUTT tJIT(HPER_n) tJIT(HPER_n+1)
1 fo
tJIT(HPER) = tJIT(HPER_n) -
1 2xfo
Figure 7: Half-Period Jitter
80%
80% VID VOD
20% Clock Inputs and outputs tSLR
20% tSLF
Figure 8: Input and Output Slew Rates
1177C--05/23/07
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ICS98ULPA877A Advance Information
CLK#
CLK
FBIN#
FBIN t() SSC OFF SSC ON SSC OFF SSC ON t()
t()dyn
t()dyn
t()dyn
t()dyn
Figure 9: Dynamic Phase Offset
50% VDDQ OE Y# 50% VDDQ Y. Y# Y
tEN
OE 50% VDDQ
tDIS Y 50% VDDQ Y#
Figure 10: Time Delay Between OE and Clock Output (Y, Y#)
1177C--05/23/07
11
ICS98ULPA877A Advance Information
VIA CARD
1
BEAD 0603
AVDD 4.7uF 1206 0.1uF 0603
VDDQ
2200pF 0603 AGND PLL
GND
VIA CARD
Figure 11. AVDD Filtering
*Place the 2200pF capacitors close to the PLL. *Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL). *Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8 DC max., 600 at 100MHz).
1177C--05/23/07
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ICS98ULPA877A Advance Information
C SEATING PLANE A1 T b REF 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q, and S not used) d TYP D1 Numeric Designations for Horizontal Grid
D
-e- TYP
TOP VIEW E h TYP 0.12 C E1
c REF
-e- TYP
ALL DIMENSIONS IN MILLIMETERS D 7.00 Bsc E 4.50 Bsc T Min/Max 0.86/1.00 e 0.65 Bsc ----- BALL GRID ----HORIZ VERT 6 10 Max. TOTAL 60 d Min/Max 0.25/0.45 h Min/Max 0.15/0.31 D1 5.85 Bsc E1 3.25 Bsc REF. DIMENSIONS b c 0.575 0.625 **
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, 10-0055 MO-205*, MO-225**
Ordering Information
ICS98ULPA877AHLF-T
Example:
ICS XXXX y H z LF- T
Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Temperature Grade Blank = 0C to +70C (Commercial) I = -40C to +85C (Industrial) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
1177C--05/23/07
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ICS98ULPA877A Advance Information
Seating Plane (Ref.) ND & NE Even
Index Area N
A1 A3 L
(ND - 1) x e (Ref.)
e/2 1 2 or Anvil Singulation 1 2 Sawn Singulation Top View E2 E2/2
(Typ.) If ND & NE are Even
E
(NE - 1) x e (Ref.)
b A C 0.08 C (Ref.) ND & NE Odd e D2/2 D2 Thermal Base
D
THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE
ALL DIMENSIONS IN MILLIMETERS
N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX.
40 10 10 6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 0.30 / 0.50
SYMBOL A A1 A3 b e
MIN. MAX. 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC
Source Reference: MLF2TM S
10-0053
Ordering Information
ICS98ULPA877AKLF-T
Example:
ICS XXXX y K z LF- T
Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Temperature Grade Blank = 0C to +70C (Commercial) I = -40C to +85C (Industrial) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
1177C--05/23/07
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